Cirrus Chips Combat Jitter - ProSoundNetwork.com

Cirrus Chips Combat Jitter

Austin, TX (July 18, 2005)--Cirrus Logic has developed an approach to combating A/D interface or network jitter by pairing two components already in Cirrus' inventory. Using the CS5381 analog-to-digital converter and CS8421 asynchronous sample rate converter, an analog-to-digital conversion system with an asynchronous digital decimation filter can be created that is purported as "virtually immune" to interface or network jitter. In addition, the CS8421 adds a multichannel Time Division Multiplexed (TDM) output format option and, along with the standard 24-bit audio data, adds the functionality to output properly dithered 32-, 20- or 16-bit data.
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Austin, TX (July 18, 2005)--Cirrus Logic has developed an approach to combating A/D interface or network jitter by pairing two components already in Cirrus' inventory. Using the CS5381 analog-to-digital converter and CS8421 asynchronous sample rate converter, an analog-to-digital conversion system with an asynchronous digital decimation filter can be created that is purported as "virtually immune" to interface or network jitter. In addition, the CS8421 adds a multichannel Time Division Multiplexed (TDM) output format option and, along with the standard 24-bit audio data, adds the functionality to output properly dithered 32-, 20- or 16-bit data.

This combination of features is said to address many of the issues and design challenges associated with networked audio systems and other high-performance applications. Cirrus has presented the package and usage guidelines as a user-implementable reference design designated CRD5381.

The CRD5381 was designed as a platform for easy evaluation of the jitter rejection, sample rate conversion, and time-division multiplexing capabilities of the CS8421 in the context of a A/D conversion system with an asynchronous decimation filter. The CRD5381 accepts four channels of balanced, analog audio input and provides four channels of PCM data output. The data output can be either a 4-channel TDM format or two independent stereo left-justified data outputs. The PCM data output is synchronous to the serial left-right clock and bit clock that the user supplies. The CRD5381 also provides status indicators including ADC overflow and SRC unlock, and it accepts an external reset signal. The only system power requirements for the design include +/- 12 Volts and +3.3 Volts. The required input signals are a left/right or word clock and serial clock for the audio data output.

The clock requirements of many typical conversion systems use jitter-susceptible high-speed system clocks and PLL recovery systems. The combination of the A/D and sample rate converter (SRC) provide an alternative approach by creating a system architecture where the A/D and D/A conversion nodes operate within local clock domains which are independent of the network or system clock domain. This can be accomplished with the use of an SRC, enabling the conversion processes to operate at a fixed sample rate, which is always higher than the network or interface sample rate. The fundamental advantage of this approach is that a local jitter-free crystal oscillator controls the conversion processes.

Operational instructions and schematics are available for download from the Cirrus website, along with a companion Applications Note, AN270.

Cirrus Logic
www.cirrus.com